The present application relates generally to semiconductor devices, and more specifically to vertical field effect transistors (VFETs) and their methods of production.
Vertical field effect transistors such as vertical fin FETs are devices where the source-drain current flows from a source region to a drain region through a channel region of a semiconductor fin in a direction normal to a substrate surface. An advantage of the vertical FET is its decreased footprint, which may beneficially impact device scaling relative to alternate geometries. In vertical fin field effect transistor (FinFET) devices, the fin defines the transistor channel with the source and drain regions located at opposing (i.e., upper and lower) ends of the fin.
Aggressive scaling of semiconductor devices and the attendant decrease in critical dimension (CD) poses a number of challenges, including the creation of parasitic capacitance or short circuits between adjacent conductive elements due to a decreased spacing therebetween. Accordingly, it would be beneficial to provide methods for manufacturing advanced node vertical FinFET devices having a reduced footprint without adversely affecting device performance and reliability.